This invention relates to the field of decoupling capacitors for integrated circuits. More particularly, this invention relates to novel and improved decoupling capacitors especially suitable for use in conjunction with Pin Grid Array (PGA) type integrated circuit packages and leaded and leadless chip carrier packages for surface mounted integrated circuits.
It is well known in the field of microelectronics that high frequency operation, particularly the switching of integrated circuits, can result in transient energy being coupled into the power supply circuit. Generally, the prevention of the coupling of undesired high frequency noise or interference into the power supply for an integrated circuit is accomplished by connecting a decoupling capacitor between the power and ground leads of the IC. One connection scheme utilizes a capacitor which is mounted on a multilayer printed circuit board, outside the integrated circuit with plated through holes used to connect the capacitor to the internal power and ground planes, which in turn make contact with the power supply connection leads of the integrated circuit. A less preferred method (in terms of higher inductance) is to interconnect the decoupling capacitor and integrated circuit power and ground leads via traces on either a multilayer or double sided printed circuit board.
The above two decoupling techniques suffer from several deficiencies. The most serious of these deficiencies resides in the fact that the circuits, including the capacitors, become highly inductive at high frequencies as a consequence of the shape and length of the leads and interconnection traces between the discrete capacitor and the integrated circuit which it decouples. In fact, the inductance of the leads and printed circuit board traces may be sufficiently high to nullify the high frequency effect of the capacitor in the circuit. A second serious deficiency resides in the spatial inefficiency incident to employing a capacitor adjacent to the integrated circuit. The space requirements i.e., real estate, of the decoupling capacitor and the interconnection traces on the printed circuit board adversely affect the optimum component packaging density which can be achieved on the board.
In an effort to overcome the above-discussed deficiencies associated with the use of decoupling capacitors mounted on a printed circuit board, a decoupling capacitor which is adapted to be mounted underneath a conventional dual-in-line circuit has been proposed. U.S. Pat. No. 4,502,101 (which is assigned to the assignee hereof, and the entire contents of which are incorporated herein by reference) discloses a decoupling capacitor for an integrated circuit package. The decoupling capacitor of that prior patent is a thin rectangular chip of ceramic material which is metallized on opposite sides and has two electrically active leads from the metallized coatings on opposite sides of the chip at two points adjacent a pair of diagonally opposed corners of the rectangularly shaped ceramic chip. The capacitor may also contain two or more electrically inactive dummy leads. The two active (and dummy) leads are bent downwardly, and the decoupling capacitor assembly is encapsultated in a film of non-conductive material. In accordance with the teachings of that prior patent, the decoupling capacitor is dimensioned so as to be received in the space between the two rows of leads extending from a conventional dual-in-line integrated circuit. The two electrically active leads from the decoupling capacitor are plugged into a printed circuit board, with these leads from the capacitor being inserted into the printed circuit through holes to which the ground power supply conductors are connected. The associated integrated circuit or other electronic component is then positioned over the capacitor and inserted into the board such that the power supply leads of the integrated circuit or other component will be positioned in the same through holes of the printed circuit board in which the two electrically active capacitor leads have been inserted. U.S. Pat. No. 4,636,918, which is also assigned to the assignee hereof and incorporated herein by reference, discloses a decoupling capacitor element which is mounted either above a dual-in-line integrated circuit package or on the back side of a circuit board in alignment with a dual-in-line integrated circuit package.
While suitable for its intended purposes, the decoupling capacitors described in U.S. Pat. Nos. 4,502,101 and 4,636,918 are not particularly adapted to be used in conjunction with Pin Grid Array (PGA) type integrated circuit packages or surface mounted chip carrier type integrated circuit packages of the "leaded" or "leadless" types. PGA packaging and surface mounted chip carrier packaging are becoming a commonly used IC packaging technology. As with conventional dual-in-line packages, PGA packages and surface mounted chip carrier packaging require similar decoupling across the power and ground leads. However, decoupling capacitors of the type disclosed in the above discussed patents have a structure and configuration which preclude their usage in conjunction with the distinctive configuration of well known PGA and surface mounted integrated circuit packages.
U.S. Pat. No. 4,626,958 overcomes the above problems and deficiencies by providing a decoupling capacitive structure which is particularly well suited for use in conjunction with Pin Grid Array type integrated circuit packages. Similarly, U.S. patent application Ser. No. 763,826 filed Aug. 8, 1985, now U.S. Pat. No. 4,658,327 issued Apr. 14, 1987, discloses a decoupling capacitor for use in conjunction with a surface mounted plastic leaded chip carrier. The decoupling capacitor of U.S. Ser. No. 763,826 is particularly adapted for mounting between a printed wiring board and a surface mounted integrated circuit. Finally, U.S. patent application Ser. No. 890,489 filed July 25, 1986, now U.S. Pat. No. 4,667,267, relates to a decoupling capacitor for use with a PGA package wherein the decoupling capacitor has at least one multilayer capacitive element in an effort to achieve higher capacitance values and increased temperature stability. U.S. Pat. No. 4,626,958 and U.S. patent application Ser. Nos. 763,826 and 890,489 are all assigned to the assignee hereof and the entire contents are incorporated herein by reference thereto.
While well suited for their intended purposes, there is a perceived need for decoupling capacitors for PGA packages and surface mounted chip carriers of the leaded and leadless type which have the ability to perform other important functions. For example, there is a need for a decoupling capacitor for use with surface mounted leadless and leaded chip carriers having increased capacitance by incorporation of a multilayer capacitive element therein. Also, there is a need for a decoupling capacitor for use with surface mounted leadless (as opposed to "leaded") chip carriers which can be mounted over the leadless chip carrier rather than between the chip carrier and the printed wiring board. Finally, there is also a need for decoupling capacitors for both PGA packages and surface mounted chip carriers which are comprised of metallized dielectric (i.e., ceramic) substrates which combine the decoupling function with that of a heat sink.